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[VHDL-FPGA-Verilog] ALU

Description: vhdl代码 使用quartus编译 cpu中 alu的设计 可作为课程设计的参考 此为16的运算器-VHDL code using Quartus compiler cpu in alu design of curriculum design can be used as a reference for this for 16 computing device
Platform: | Size: 1024 | Author: 闵瑞鑫 | Hits:

[ARM-PowerPC-ColdFire-MIPS] RICS_multiple_design

Description: RICS multiple design example.verilog description.risc mcu
Platform: | Size: 343040 | Author: chren | Hits:

[VHDL-FPGA-Verilog] Chapter10

Description: 第十章的代码。 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示-Chapter X code. This book by more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of additions device/counters, multipliers/dividers, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and the results demonstrate
Platform: | Size: 6872064 | Author: xiao | Hits:

[VHDL-FPGA-Verilog] sequencecontroller

Description: this is source code in verilog for sequence controller and clock generator which is used in RISC cpu
Platform: | Size: 99328 | Author: Harshit B J | Hits:

[VHDL-FPGA-Verilog] risc8

Description: 8 bit risc code with verilog
Platform: | Size: 50176 | Author: richard | Hits:

[VHDL-FPGA-Verilog] risc8

Description: 基于verilog的8位risc-cpu源码，modelsim仿真-Verilog-based 8-bit risc-cpu source, modelsim simulation
Platform: | Size: 618496 | Author: 文婷 | Hits:

[VHDL-FPGA-Verilog] sparc_verilog

Description: open risc微处理器的verilog源码。基于sparc架构，可以直接综合。适合cpu的学习-open risc microprocessor verilog source. Based on sparc architecture can be directly integrated. Learning for the cpu
Platform: | Size: 214016 | Author: 王翔 | Hits:

[VHDL-FPGA-Verilog] risc_mod

Description: RISC controller code in verilog working code-RISC controller code in verilog working code--VVV
Platform: | Size: 70656 | Author: hr | Hits:

[VHDL-FPGA-Verilog] mips_project

Description: 我用verilog写的risc指令集的mips的cpu。可以支持定点运算。顶层单元是top。-I used to write verilog mips risc instruction set of the cpu. To support fixed-point arithmetic. Top-level unit is the top.
Platform: | Size: 17408 | Author: yangxinghua | Hits:

[VHDL-FPGA-Verilog] 8_RISC_CPU

Description: risc-cpu，简单的cpu设计,强大的功能简洁的设计，精简化-verilog risc_cpu
Platform: | Size: 9216 | Author: 王侠 | Hits:

[VHDL-FPGA-Verilog] clk_gen.v

Description: 时钟发生器，用计数器功能编写的，能更好的潜入模块中,risc-cpu的一部分-clk_gen verilog
Platform: | Size: 3137536 | Author: 王侠 | Hits:

[VHDL-FPGA-Verilog] risc_cpu-OK

Description: 夏宇闻 verilog数字系统设计教程源码 第二版，实现了简单的RISC CPU。印刷版有误，已改正。- A simple RISC CPU Verilog HDL source code. Work well.
Platform: | Size: 9216 | Author: Jian SUN | Hits:

[VHDL-FPGA-Verilog] pic10_verilog

Description: 用verilog实现了PIC10系列单片机的IP核，代码基本来自一篇国外的文章《A Microchip PIC-Compatible RISC CPU IP Core Design and Verilog Implementation》，对一部分进行了改进，主要包括对原文中有一些不可综合的@（posedge clk）语句的改写，使其能通过quartus的编译和综合，并且对跳转部分增加了比较多的注释，这篇文章写得非常好，感谢这篇文章的作者John Gulbrandsen先生，这篇文章让我学到了很多-PIC10 CPU IP Core Verilog Implementation reference:John Gulbrandsen 《A Microchip PIC-Compatible RISC CPU IP Core Design and Verilog Implementation》
Platform: | Size: 3459072 | Author: panpan | Hits:

[ARM-PowerPC-ColdFire-MIPS] BuildingPaPRISCPSystemPinPanPFPGA

Description: 一个32位 RISC CPU 核心，由Verilog 编写而成-A 32-bit RISC CPU core, written by Verilog
Platform: | Size: 361472 | Author: QINZ | Hits:

[VHDL-FPGA-Verilog] ASSIGNMENT3

Description: Implementation of risc processor program in verilog coding.-Implementation of risc processor program in verilog coding.
Platform: | Size: 118784 | Author: poo | Hits:

[Other] Verilog_RISC_CPU

Description: 可综合的verilog描述的精简指令集的cpu设计-Verilog description integrated RISC CPU design
Platform: | Size: 394240 | Author: david | Hits:

[VHDL-FPGA-Verilog] all_cpu

Description: 精简指令集CPU，可完成移位，跳转等简单功能，适用于FPGA学习，本代码使用verilog编写。-RISC CPU, to be completed by the shift, jumps and other simple functions for FPGA learning to write the code using verilog.
Platform: | Size: 1884160 | Author: 晓东 | Hits:

[Other] DLX_verilog

Description: DLX指令集RISC CPU verilog源码，使用哈佛结构可实现十多种指令-DLX instruction set RISC CPU verilog source code, using the Harvard architecture can achieve more than ten kinds of instruction
Platform: | Size: 3072 | Author: 石建刚 | Hits:

[VHDL-FPGA-Verilog] risc64

Description: Risc 64 - Bit Verilog Code
Platform: | Size: 1024 | Author: thannasantosh | Hits:

[VHDL-FPGA-Verilog] openfire_core_latest.tar

Description: openfire实现 microblaze机构的cpu代码,RISC CPU 的Verilog 设计源码，可综合。内含详细的设计文挡-openfire complete microblaze architecture cpu,RISC CPU Verilog sourcecode and documents
Platform: | Size: 37888 | Author: 将 | Hits:
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